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[Other resource] 标准SDR SDRAM控制器参考设计_verilog_lattice

Description: 标准SDR SDRAM控制器参考设计，Lattice提供的verilog源代码-standard SDR SDRAM controller reference design, the Lattice Verilog source code
Platform: | Size: 204299 | Author: 陈旭 | Hits:

[Other resource] sdr sdram controller

Description: ALTERA sdram vhdl与verilog参考设计-Altera SDRAM VHDL and Verilog reference design
Platform: | Size: 2459435 | Author: 陈东平 | Hits:

[Other resource] ref-sdr-sdram-verilog

Description: 本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.
Platform: | Size: 776597 | Author: 汪旭 | Hits:

[Other resource] very-good-ok-ref-ddr-sdram-verilog

Description: Sdr SDRAM控制器参考设计,很好的-Sdr SDRAM controller reference design, very good
Platform: | Size: 895594 | Author: 姚明 | Hits:

[VHDL-FPGA-Verilog] ddr_verilog_xilinx

Description: DDR（双速率）SDRAM控制器参考设计，xilinx提供-DDR (double data rate) SDRAM controller reference design for Xilinx
Platform: | Size: 131072 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] ARM9_instruction_cache_verilogCodes

Description: Arm9指令Cache缓存模块的verilog代码，对一些做ARM硬件开发的朋友有参考价值。-Arm9 Instruction Cache Cache Module Verilog code, do some of the hardware development of the ARM friends reference value.
Platform: | Size: 3072 | Author: 杨力 | Hits:

[VHDL-FPGA-Verilog] CommandResponse

Description: verilog语言写的sdram控制器—命令响应模块代码，经过测试，逻辑正确，可编译，可综合-verilog language written sdram controller-order response to the code, tested, logically correct, compiler, integrated
Platform: | Size: 1024 | Author: hanjian | Hits:

[VHDL-FPGA-Verilog] control_interface

Description: SDRAM控制器Verilog员代码，控制接口模块，完成和顶层模块的控制命令的传递-SDRAM controller member Verilog code control interface module, Top module and complete the transfer of control orders
Platform: | Size: 3072 | Author: 陈建勇 | Hits:

[VHDL-FPGA-Verilog] Commandinterface

Description: SDRAM控制器Verilog员代码，命令生成模块，完成SDRAM控制接口命令的生成-SDRAM controller member Verilog code, order generation module, SDRAM interface complete control orders Generation
Platform: | Size: 7168 | Author: 陈建勇 | Hits:

[VHDL-FPGA-Verilog] sdram_controller

Description: sdram控制器，经过时序仿真，功能正确-SDRAM controller, after timing simulation, the correct function
Platform: | Size: 31744 | Author: 雷峰成 | Hits:

[ARM-PowerPC-ColdFire-MIPS] mem_ctrl.tar

Description: verilog 写的 memory controller ，可以控制SDRAM SRAM NOR -written in Verilog memory controller, can control SDRAM SRAM NOR
Platform: | Size: 331776 | Author: youjia | Hits:

[VHDL-FPGA-Verilog] xapp134_vhdl

Description: The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM models. The design is verified with timing constraints at 115 MHZ.-err
Platform: | Size: 2628608 | Author: ronsullivan | Hits:

[Software Engineering] DDR_SDRAM_controller_verilog

Description: DDR SRAM控制器的verilog完整设计文档（包含有完整的verilog源代码），-DDR SRAM controller complete Verilog design documents (including a complete Verilog source code),
Platform: | Size: 475136 | Author: lipengfei | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: verilog 128位 突发4. sdr fpga控制器-verilog 128 bit unexpected 4. sdr fpga controller
Platform: | Size: 119808 | Author: pudnrtest | Hits:

[VHDL-FPGA-Verilog] SDRAM-control

Description: SDRAM控制器的Verilog源代码，主要用于SDR-SDRAM-SDRAM controller
Platform: | Size: 2824192 | Author: 金文超 | Hits:

[VHDL-FPGA-Verilog] sdr_sdram

Description: sdram控制器，verilog语言写的-sdram controller, verilog language to write
Platform: | Size: 2048 | Author: xwj | Hits:

[VHDL-FPGA-Verilog] SDRAM-Verilog-HDL

Description: SDRAM控制器Verilog HDL-source-code.rar-SDRAM-controller-Verilog HDL-source-code.rar
Platform: | Size: 719872 | Author: 小单 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: sdram控制器的Verilog描述 测试可用-the sdram controller Verilog description of test available
Platform: | Size: 8192 | Author: 刘备 | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: Verilog HDL 语言构建SDRAM 控制器的详细方案设计-SDRAM controller Verilog HDL language construct detailed program design
Platform: | Size: 9984000 | Author: 刘明来 | Hits:

[VHDL-FPGA-Verilog] DDR-SDRAM-Controller

Description: DDR SDRAM控制器verilog代码及中文说明文档-DDR SDRAM Controller Using Virtex-5 FPGA Devices
Platform: | Size: 262144 | Author: 马龙 | Hits:
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